To simulate electronic circuits, transistor models are used that inherently represent a simplified version of reality. However, as complexity and performance requirements increase, more and more effects must be taken into account.
The speakers of the first presentation - Tobias Gnos from the Institute for Computational Engineering ICE and Lukas Leuenberger from IMES - presented their approach to simulating mechanical stress on semiconductors. The expertise of both institutes played a key role: Tobias Gnos simulated the distribution of mechanical stress on the silicon die within the package using FEM simulations, while Lukas Leuenberger adapted the transistor models so that stress can be included as an additional parameter. Based on the transistor’s position on the ASIC, the corresponding local stress parameter is then calculated. This allows mechanical stress to be incorporated into electrical simulation.
The second presentation, given by Nicolas Vetsch from the Institute for Integrated Systems IIS at ETH Zurich, focused on transistors that do not yet exist: IIS aims to predict the behavior of novel devices through simulations at the atomic level. Since the development of transistors in cutting-edge semiconductor processes is complex and costly, simulating the components helps reduce the number of expensive iteration cycles. Structures of only a few nanometers in size are simulated, where only quantum mechanics can provide reliable results. Despite their tiny volumes, these structures still consist of several tens of thousands of atoms whose complex equations must be solved. And even though IIS researchers have access to the world’s fastest supercomputers, they must optimize their algorithms at every level to obtain results within a reasonable time. Nicolas Vetsch’s talk offered a fascinating look into the world of the smallest transistors—and simultaneously into the world of the enormous computers built from them.
The subsequent apéro gave rise to lively discussions about the two exciting presentations.